Using VHDL for link to synthesis tools
| Author(s) : | Mohammed Belhadj, |
| Publisher : | N/A |
| Publication Date : | 1994 |
| ISSN : | N/A |
| Abstract : | This paper presents the work done to use industry and academic synthesis tools for the hardware-software codesign of reactive systems. It emphasizes the hardware synthesis and design part by linking SIGNAL and VHDL. The SIGNAL language is used for system specification and VHDL for the link to synthesis tools. To permit a maximum of flexibility, different strategies for linking are described., |