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Abstract : |
Field Programmable Gate Arrays (FPGAs) provide a new approach to Application Specific Integrated Circuit (ASIC) implementation that features both large scale integration and user programmability. The logic capacity of these devices is large enough to make automated synthesis essential for the efficient design of FPGA circuits. This thesis focuses on the class of FPGAs that use lookup tables (LUTs) to implement combinational logic. A K-input lookup table is a digital memory that can implement any Boolean function of K variables. Lookup table circuits present new challenges for logic synthesis, particularly technology mapping, which is the phase of logic synthesis directly concerned with the selection of the circuit elements to implement the final circuit. Conventional library-based technology mapping has difficulty with lookup table circuits because each lookup table can implement a large number of different functions. This thesis presents two new technology mapping algorithms that construct circuits of K-input lookup tables from networks of ANDs, ORs and NOTs. The first, |
