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Abstract : |
A single-chip ?xed-point vector microprocessor is described. The chip contains a MIPS-II RISC core with a 1KB instruction cache, dual eight-way parallel vector arithmetic pipelines, a 128-bit memory interface, and an 8-bit serial host interface. Each vector arithmetic pipeline contains a cascade of six functional units that can be dynamically recon?gured by each instruction. The resulting peak performance is 4.3 billion 32-bit arithmetic operations per second at a clock speed of 45 MHz. 1, |
