Specification issues for real-time behaviour of RISC processors
| Author(s) : | Peter Kearney Peter Kearney Mark Utting Mark Utting, |
| Publisher : | N/A |
| Publication Date : | 1994 |
| ISSN : | N/A |
| Abstract : | This report presents an overview of some of the main issues relevant to the task of specifying the real-time behaviour of various commercially available RISC architectures. These issues were investigated during the first stage of a project to formally verify the real-time behaviour of interruptdriven code for a modern RISC architecture. Part of this first stage was to select an architecture for investigation. A result of the investigation was the selection of the MIPS 1, |