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Abstract : |
Abstract ? Cryptograpfdcaf applications demand both high speed and high security. This paper presents the implementation of a new high-per-formance Data Encryption Standard (DES) data encryption chip. It is the result of close cooperation between cryptographers and chip designers. At the system design level, cryptograpfdcal optimization and equivalence transformations lead to a very efficient floor plan with minimal routing, which otherwise wonld present a serious problem for data scrambling algorithms. These optfmizations, which do not compromise the DES algorithm nor the security, are combined with a highly structured design and layout strategy. Novel CAD tools are nsed at different steps in the design process. The resnft is a single chip of 25 mmz in 3- pm double-metal CMOS, Functionality tests show that a clock of 16.7 MHz can be applied, which means that a 32-Mbk/s data rate can be achieved for all eight byte modes. This is the fastest DES chip reported yet, aflowing equally fast execution of all four DES modes of operation due to an originaf pipeline architecture. 1., |
