Parallelization of loops with exits on pipelined architectures
| Author(s) : | P. Tirumalai Michael Schlansker Meng Lee Parthasarathy Tirumalai M. Lee M. Schlansker, |
| Publisher : | N/A |
| Publication Date : | 1990 |
| ISSN : | N/A |
| Abstract : | conditional execution; dependence graphs; loop scheduling; modulo scheduling; performance bounds; pipelined architectures; software pipelining; while loops To be published inthe proceedings of SuperComputing ' 90,, |