|
Abstract : |
In ICCAD88, we had proposed an efficient parallel algorithm PACE to speed up the first phase of VLSI circuit extraction, called the net list extraction phase. In this paper, we describe an algorithm PACE2 targeted to the second phase of extraction, called the parameter extraction phase. We have interfaced two models for resistance and capacitance. In this paper, we also propose a different partitioning scheme, namely by equal number of rectangles, so as to balance the load. The parallel algorithm has been implemented on the Intel iPSC2/D4-MX hypercube., |
