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Abstract : |
Look-Up Table (LUT) method for inverse halftoning is computation less, fast, and also yields goods results. It employs a single LUT that is stored in a ROM and contains pre-computed contone (gray level) values for inverse halftone operation. This paper proposes an algorithm that can perform parallel inverse halftone operation by partitioning the single LUT into N smaller Look-Up Tables (s-LUTs). Thereby, upto k (k≤N) pixels can be concurrently fetched from the halftone image, and their contone values can also be fetched concurrently from separate smaller Look-Up Tables (s-LUT). The parallelization increases the speed of inverse halftoning by upto k times while the total entries in all s-LUTs remains equal to the entries in the single LUT of the serial LUT method. Some degradation in image quality is possible due to pixel loss during parallel fetching. This is due to some contone values cannot be fetched in the same cycle because some other contone value is being fetched from the s-LUT. The complete implementation of the algorithm requires two CPLD devices for computational portion, external content addressable memories (CAM) and static RAMs to store s-LUTs., The Look-Up Table (LUT) method for inverse halftoning is not only computation-less and fast but yields good results. The method employs a single LUT that is stored in a ROM and contains pre-computed contone (gray level) values for inverse halftone operation. This paper proposes an algorithm that call perform parallel inverse halftone operations by partitioning the single LUT into AT smaller Look-Up Tables (s-LUTs). Therefore, Lip to k (k <= N) pixels can be concurrently fetched from the halftone image and their contone values fetched concurrently from separate sLUT. Obviously, this parallelization increases the speed of inverse halftoning, by Lip to k times. In this proposed method, the total entries in all s-LUTs remain equal to the entries in the single LUT of the serial LUT method. Some degradation in image quality is possible due to pixel loss during parallel fetching. This is because Some contone values cannot be fetched in the same cycle because some other contone value is being fetched from that s-LUT. The complete implementation of the algorithm requires two CPLDs (Complex Programmable Logic Devices) for the computational portion, external content addressable memories (CAM) and static RAMs to store s-LUTs., |
