Mostafa__Abd-El-Barr
A Frontier algorithm for optimization of multiple-valued logic functions
A Frontier algorithm for optimization of multiple-valued logicfunctions
A hierarchical fault-tolerant interconnection network
A high-performance hardware-efficient memory allocation techniqueand design
A hybrid scheme for tolerating mobile support station failures
A LOW POWER REMOTE DATA ACQUISITION CONTROL MODULE FOR OIL INDUSTRY
A modified ant colony algorithm for evolutionary design of digital circuits
A modified ant colony algorithm for evolutionary design of digital circuits
A new algorithm for RNS decoding
A new improved cost-table-based technique for synthesis of 4-valued unary functions implemented using current-mode CMOS circuits
A new improved cost-table-based technique for synthesis of 4-valuedunary functions implemented using current-mode CMOS circuits
A self-organizing neural network using cascaded Adaptive Resonance Theory (CART)
A survey and comparison of wormhole routing techniques in a meshnetworks
A survey and comparison of wormhole routing techniques in mesh networks
Analysis of direct cover algorithms for minimization of MVL functions
Cost-analysis of 4-valued unary functions implemented using current-mode CMOS circuits
Cost-analysis of 4-valued unary functions implemented usingcurrent-mode CMOS circuits
Digital circuit design through simulated evolution (SimE)
Fault characterization and testability considerations in Multi-Valued logic circuits
Fault characterization and testability considerations inmulti-valued logic circuits
Fault tolerance in topological optimization of computer networks
Fault-tolerance and terminal reliability for a class of datamanipulator networks
Fault-tolerant neural network with concurrent error detection and correction capability
Fuzzified ant colony optimization algorithm for efficient combinational circuits synthesis
Iterative-based minimization of unary 4-valued functions for current-mode CMOS realization
Iterative-based minimization of unary 4-valued functions for current-mode CMOS realization
Less expensive test pattern generation technique
New MVL-PLA structures based on current-mode CMOS technology
On the use of fuzzy logic in a hybrid scheme for tolerating mobile support station failure
On the use of fuzzy logic in a hybrid scheme for tolerating mobilesupport station failure
Reliability and fault tolerance based topological optimization of computer networks - Part I: Enumerative techniques
Reliability and fault tolerance based topological optimization of computer networks - Part II: Iterative techniques
Reliability and fault tolerance based topological optimization of computer networks - part I: enumerative techniques
Reliability and fault tolerance based topological optimization of computer networks - part II: iterative techniques
Statistical analysis of multiple intermittent faults in combinational circuits
Subcube reliability of a modular fault-tolerant hypercube architecture
Synthesis of multiple-valued decision diagrams using current-modeCMOS circuits
Synthesis of MVL functions - part 1: The genetic algorithm approach
Synthesis of MVL Functions - Part I: The Genetic Algorithm Approach
Synthesis of MVL functions using input and output assignments
Transistor stuck-open fault detection in multilevel CMOS circuits
VLSI considerations in the design of k-ary n-cube interconnectionnetworks