Jordi__Cortadella
A mathematical formulation of the loop pipelining problem
A region-based theory for state assignment in speed-independent circuits
Complete state encoding based on the theory of regions
Decomposition and technology mapping of speed-independent circuits using boolean relations
Lazy transition systems and asynchronous circuit synthesis with relative timing assumptions
Logic synthesis techniques for embedded control code optimization
Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions