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Abstract : |
In multiprocessors, caching is an effective latency reducing technique. However, adding caches to a multiprocessor system also introduces the cache coherence problem. Many different solutions to this problem have been proposed and implemented. This work focuses on the design of hardware controllers that enforce cache coherence, enable non-coherent operations, uncached operations and special functions in the NUMAchine multiprocessor. The con-troller logic is functionally decomposed into simpler components which enables an efficient and flexible implementation in field-pro-grammable devices (FPDs). The controllers have been built and tested to run at a clock rate of 50 MHz. This implementation of hardware cache coherence provides a good trade-off between cost, flexibility and performance, placing it between implementations using custom hardware and those using commodity parts. ii Acknowledgements I would like to thank my supervisors Dr. Z. G. Vranesic and Dr. S. Srbljic for their advice, guidance and encouragement. They have introduced me to multiprocessors, cache coherence and NUMA-chine. Without them, this work would not have been possible. I am indebted to them both. A deserved thanks goes to the other members of the NUMA-chine project. Their help with implementation, simulation and debugging is greatly appreciated. I would like to thank my family for their love, support, and sac-rifices. They have always had faith in me and stood behind what-ever I chose to do. A very special thank you goes to Gordana for her love, understanding, and dedication throughout all the hard work. Many thanks go to my friends both inside and outside the Com-puter and Electronics Group for making the last two years as much fun as they have been. I express my thanks to Steve Caranci, Derek, |
