Formal specification and simulation of instruction-level parallelism
| Author(s) : | Todd Cook Jon Mauney, |
| Publisher : | N/A |
| Publication Date : | 1994 |
| ISSN : | N/A |
| Abstract : | In this paper we show how to formally specify and simulate the high-level instruction timing properties of RISC/Superscalar instruction set processors. We illustrate the technique using a hypothetical processor that includes many features of commercial processors including delayed loads and branches, interlocked floating-point instructions, and multiple instruction issue. As our formalism we use SCCS, a synchronous process algebra designed for specifying timed, concurrent systems. 1, |