Design and implementation of the SNAP floating-point adder
| Author(s) : | Michael Flynn Michael Flynn Nhon Quach Nhon Quach Nhon Quach Michael Flynn, |
| Publisher : | N/A |
| Publication Date : | 1991 |
| ISSN : | N/A |
| Abstract : | This paper describes the design and implementation of the floating-point adder in the Stanford Nanosecond Arithmetic Processor (SNAP). The adder is capable of adding two double precision IEEE numbers in less than 20ns nominal with all IEEE rounding modes. Only round to nearest is described in this paper, however. The adder has been laid out in the HP CMOS26 1m process with triple-layer metal, occupying a silicon area of roughly, |