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Blocking linear algebra codes for memory hierarchies


Author(s) : Ken Kennedy Steve Carr, 
Publisher : N/A
Publication Date : 1989
ISSN : N/A
Abstract : Abstract. Because computation speed and memory size are both increasing, the latency of memory, in basic machine cycles, is also increasing. As a result, recent compiler research has focused on reducing the effective latency by restructuring programs to take more advantage of high-speed intermediate memory (or cache, as it is usually called). The problem is that many real-world programs are non-trivial to restructure, and current methods will often fail. In this paper, we present some encouraging preliminary results of a project to determine how much restructuring is possible with automatic techniques. 1. Introduction. Over,