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Abstract : |
c fl Copyright by Keith Farkas 1991 A decentralized, hierarchical cache-consistency scheme is presented. This scheme is targeted for shared-memory multiprocessors consisting of processor and memory modules interconnected by a hierarchy of ring-connected buses. It is shown that this scheme enforces sequential consistency without the need for complex hardware or complicated protocols. The proposed scheme relies on snooping and the inherent broadcast nature of the rings and station buses. Because responsibility for maintaining consistency lies with the cache and bus controllers, the scheme is scalable. In the development of the consistency scheme, several assumptions are made about the interconnect structure and the processing modules. By examining these assumptions in the context of the Hector multiprocessor, it is shown that the scheme can be used to enforce sequential consistency in a real multiprocessor. Finally, using address-trace-driven simulations, it is shown that the performance of Hector would not be adversely affected by the use of this consistency scheme., |
