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Abstract : |
Much emphasis is now placed on chip-multiprocessor (CMP) architectures for exploiting threadlevel parallelism in an application. In such architectures, speculation may be employed to execute applications that cannot be parallelized statically. In this paper, we present an ecient CMP architecture for speculative execution of sequential binaries without source re-compilation. We present the software support that enables identication of threads from a sequential binary. The hardware includes a memory disambiguation mechanism that enables the detection of inter-thread memory dependence violations during speculative execution. This hardware is dierent from past proposals in that it does not rely on a snoopy-based cache-coherence protocol. Instead, it uses an approach similar to a directory-based scheme. Furthermore, the architecture includes a simple and ecient hardware mechanism to enable register-level communication between on-chip processors. Evaluation of this software-hardware approach shows that it is quite eective in achieving high performance when running sequential binaries. Keywords: Chip-multiprocessor, speculative multithreading, data-dependence speculation, control speculation, |
