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Abstract : |
Abstract ? A high speed CMOS signaling interface for application in multiprocessor interconnection networks has been developed. The interface utilizes 1-V push?pull drivers, a delay line phase-locked loop (PLL), and sampling of the data on both edges of the clock. In order to increase the noise immunity of the reception, a current-integrating input pin sampler is used to receive the incoming data. Chips fabricated in a 0.8-"m CMOS technology achieve transfer rates of 740 Mb/s/pin operating from a 3.3-V supply with a bit error rate of less than 100IR. Index Terms ? Data communication, delay line phase-locked loop, digital communication, interchip communication, integrated circuit interconnections, integrated circuits, integrating receivers, mixed-signal integrated circuits. I., |
