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Abstract : |
Abstract?This paper describes voltage and timing margins and design trade-offs in low-cost parallel links. Results from a transceiver prototype demonstrate that per-pin skew compensation improves timing margins in these parallel links and can be implemented with reasonable cost overhead. Single-ended and simultaneous bidirectional links are viable alternatives to the traditional differential and unidirectional systems?these links require fewer pins and wires for the same bandwidth, and the additional noise sources, while significant, can be managed by careful circuit and package design. Index Terms?Parallel links, simultaneous bidirectional links, single-ended links, skew compensation, timing error, voltage noise. I., |
